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Wednesday 27 April 2016

Semester S6 CS6303



CS6303 – COMPUTER ARCHITECTURE - Anna University Question Paper


Question Paper Code : 80289
B.E / B.Tech Degree Examination , November / December 2016
Sixth Semester
Electronics and Communication Engineering
CS6303 – COMPUTER ARCHITECTURE
(Regulation 2013)
Time : Three hours                                                                                          Maximum: 100 marks
Answer ALL Questions
PART A – (10 * 2 =20 marks)
1.      What is an instruction register?
2.      Give the formula for CPU execution time for a program.
3.      What is a guard bit and what are the ways to truncate the guard bits?
4.      What is arithmetic overflow?
5.      What is meant by pipeline bubble?
6.      What is a data path?
7.      What is instruction level parallelism?
8.      What is multithreading?
9.      What is meant by address mapping?
10.  What is cache memory?

PART B – (5 * 13 = 65 marks)
11.       (a) Explain in detail the various components of computer system with neat diagram.
OR
            (b) Explain the different types of Addressing modes with suitable examples.

12.       (a) Explain Booths Algorithm for the multiplication of signed two’s complement numbers.
OR
            (b) Discuss in detail about division algorithm in detail with diagram and examples.

13.       (a) Why is branch prediction algorithm needed? Differentiate between the static and dynamic techniques.
OR
            (b) Explain how the instruction pipeline works. What are the various situations where an instruction pipeline can stall?

14.       (a) Explain in detail about Flynns classification of parallel hardware.
OR
            (b) Discuss Shared memory multiprocessor with a neat diagram.

15.       (a) Discuss DMA controller with block diagram.
OR
(b) Discuss the steps involved in the address translation of virtual memory with necessary block diagram.

PART C – (1* 15 = 15 marks)
16.       (a) What is the disadvantage of Ripple carry addition and how it is overcome in carry look ahead adder and draw the logic circuit CLA.
OR

            (b) Design and explain a parallel priority interrupt hardware for a system with eight interrupt sources.


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Question Paper Code : 57241
B.E / B.Tech Degree Examination , May / June 2016
Sixth Semester
Electronics and Communication Engineering
CS6303 – COMPUTER ARCHITECTURE
(Regulation 2013)
Time : Three hours                                                                                          Maximum: 100 marks

Answer ALL Questions
PART A – (10 * 2 =20 marks)
  1. How to represent Instruction in a Computer System?
  2. Distinguish between auto increment and auto decrement addressing mode.
  3. Define ALU.
  4. What is Subword Parallelism?
  5. What are the advantages of pipelining?
  6. What is Exception?
  7. State the need for Instruction Level parallelism.
  8. What is Fine grained Multithreading?
  9. Define Memory hirerachy.
  10. State the advantages of virtual memory.

PART B – (5 * 16 = 80 marks)
11.       (a) Discuss about the various components of a computer system. (16)
OR
            (b) Elaborate the different types of addressing modes with a suitable example.(16)

12.       (a) Explain briefly about floating point addition and Subtraction algorithms.(16)
OR
            (b) Define Booth Multiplication algorithm with suitable example. (16)

13.       (a) What is pipelining? Discuss about pipelined data path and control. (16)
OR
            (b) Briefly explain about various categories of hazards with examples. (16)

14.       (a) Explain in detail about Flynn’s classification. (16)
OR
            (b) Write short notes on: (16)
                        (i) Hardware multithreading
                        (ii) Multicore processors

15.       (a) Define Cache Memory? Explain the various Mapping Techniques associated with    cache memories. (16)
OR
            (b) Explain about DMA controller with the help of a block diagram. (16)




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