EC8691 Microprocessors and Microcontrollers - UNIT I

 EC8691 Microprocessors and Microcontrollers - UNIT I

1. A Machine language instruction format consists of (b)

a)       A. Operation code field

b)       B. Operation code field & operand field

c)       C. Operand field

d)       D. None of the mentioned

Answer: B

2. The left side of any binary number is called: 

            a. Least significant digit

            b. Most significant digit 

            c. Medium significant digit

            d. low significant digit

Answer: B

 

3. NMI stand for:     

            a. Non mask able interrupt

            b. Non mistake interrupt  

            c. Both  

            d. None of these

Answer: A

 

4.  ALE stand for:

a. Address latch enable

b. Address light enable

c. Address lower enable

d. Address last enable

Answer: A

 

5.  DIP stand for: 

a. Deal inline package

b. Dual inline package

c. Direct inline package  

d. Digital inline package  

Answer: B

 

6. 8086 Microprocessor supports _______ modes of operation.

A. 2
B. 3
C. 4
D. 5

Ans : A

Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

7. Which of the following is not a Features of 8086?

A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.

Ans : D

Explanation: It has 256 vectored interrupts is true Features of 8086.

 

8. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB

Ans : B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

9. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit

Ans : C

Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.

10. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?

A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag

Ans : B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.

11. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag

Ans : D

Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.

12. It is an edge triggered input, which causes an interrupt request to the microprocessor.

A. NMA
B. INTR
C. INTA
D. ALE

Ans : A

Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an interrupt request to the microprocessor.

13. It is used to write the data into the memory or the output device depending on the status of M/IO signal.

A. IR
B. HLDA
C. HR
D. WR

Ans : D

Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output device depending on the status of M/IO signal.

14. Which intruction is Used to load the address of operand into the provided register?

A. LEA
B. LDS
C. LES
D. LAHF

Ans : A

Explanation: LEA : Used to load the address of operand into the provided register.

 

15. The different ways in which a source operand is denoted in an instruction is known as

A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes

Ans : D

Explanation: The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different addressing modes in 8086 programming

 

16. The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned
Answer: d
Explanation: The CPU of 80286 contains the same set of registers as in 8086.

 

17. The bits that are modified according to the result of the execution of logical and arithmetic instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned
Answer: c
Explanation: The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the result of the execution of logical and arithmetic instructions. These are called as status flag bits.

18. The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned
Answer: b
Explanation: The flags such as trap flag (TF) and Interrupt flag (IF) bits are used for controlling the machine operation, and thus they are called control flags.

19. The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned

Answer: d
Explanation: The additional fields available in 80286 flag register are, I/O Privilege field, nested task flag, protection enable, and monitor processor extension.

 

20. Which of the block is not considered as a block of an architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit
Answer: d
Explanation: The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.

 

21. The unit that is responsible for calculating the address of instructions, and data that the CPU wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit
Answer: b
Explanation: The address unit is responsible for calculating the address of instructions, and data that the CPU wants to access. Also, the address lines derived by this unit may be used to address different peripherals.

 

22. The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing
Answer: c
Explanation: The instructions are fetched in advance and stored in a queue to enable faster execution of the instructions. This concept is known as instruction pipelining.

23. The CPU must flush out the prefetched instructions immediately following the branch instruction in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned

Answer: b
Explanation: In case of unconditional branch, the CPU will have to flush out the prefetched instructions, immediately following the branch instruction.

 

24. The device that interfaces and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d) data transreceiver
Answer: d
Explanation: The data transreceivers interface and control the internal data bus with the system bus.

 

25. The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned
Answer: d
Explanation: The execution unit contains the register bank, used for storing the data as scratch pad, or used as special purpose registers.

 

26. Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned
Answer: d
Explanation: The interrupts generated by 80286 may be divided into 3 categories as external or hardware interrupts, INT instruction or software interrupts and interrupts generated by exceptions.

 

27. For which of the following instruction does the return address point to instruction causing an exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned
Answer: d
Explanation: For the instructions, divide error, bound range exceeded and invalid opcode exceptions, the return address points to the instruction causing exception.

 

28. The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt
Answer: c
Explanation: Single step interrupt is an internal interrupt that comes into action if the trap flag (TF) is set.

 

29. The interrupt that has the highest priority among the following is
a) Single step
b) NMI (non-maskable interrupt)
c) INTR
d) Instruction exception
Answer: d
Explanation: The instruction exception has the highest priority followed by single step, NMI and INTR instrution.

 

30. The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI
Answer: c
Explanation: The INT instruction has the lowest priority. The order of priority of interrupts from high to low is
1) instruction exception
2) single step
3) NMI
4) processor extension segment overrun
5) INTR
6) INT instruction.

 

31. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.

 

32. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the carry flag, auxiliary flag and overflow flag are undefined.

 

33. The instruction that performs logical AND operation and the result of the operation is not available is
a) AAA
b) AND
c) TEST
d) XOR
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are affected.

 

34. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag.

 

35. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX becomes zero, the execution proceeds to the next instruction in sequence.

 

36. Match the following

A) MOvSB/SW       1) loads AL/AX register by content of a string

B) CMPS           2) moves a string of bytes stored in source to destination

C) SCAS           3) compares two strings of bytes or words whose length is stored in CX register

D) LODS           4) scans a string of bytes or words

a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.

 

37. The instructions that are used to call a subroutine from the main program and return to the main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Answer: c

Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.

 

38. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are not affected by this instruction.

 

39. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the ‘halt’ state.

 

40. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the clock cycle and thus there exists a delay.

 

41. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag.

 

42. The assembler directives which are the hints using some predefined alphabetical strings are given to
a) processor
b) memory
c) assembler
d) processor & assembler
Answer: c
Explanation: These directives help the assembler to correctly understand the assembly language programs to prepare the codes.

 

43. The directive used to inform the assembler, the names of the logical segments to be assumed for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.

 

44. Match the following

   a) DB          1) used to direct the assembler to reserve only 10-bytes

   b) DT          2) used to direct the assembler to reserve only 4 words

   c) DW          3) used to direct the assembler to reserve byte or bytes

   d) DQ          4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2

Answer: d
Explanation: These directives are used for allocating memory locations in the available memory.

 

45. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: b
Explanation: The directive END is used to denote the completion of the program.

 

46. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is used to end the program.

 

47. The directive that updates the location counter to the next even address while executing a series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
Answer: b
Explanation: The directive updates location counter to next even address if the current location counter contents are not even.

 

48. The directive that directs the assembler to start the memory allotment for a particular segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.

 

49. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.

 

49. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed instead of the numerical value in the entire program code.

 

50. The labels or constants that can be used by any module in the program is possible when they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by any module in the program.

 

51. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d) none of the mentioned
Answer: c
Explanation: The logic required for implementing a program must be visualized clearly which is possible by flowchart and algorithm.

52. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
Answer: b
Explanation: Only one memory operand can be specified in one instruction.

53. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H

Answer: c
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.

 

54. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
Answer: d
Explanation: Both the operands cannot be memory operands.

 

55. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
Answer: c
Explanation: Since destination operand should not be immediate data.

 

56. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
Answer: d
Explanation: Segment registers are not allowed as operands for arithmetic and logical instructions.

 

57. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
Answer: b
Explanation: Both the operands should not be immediate operands and memory operands.

 

58. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned

Answer: d
Explanation: The machine level programming is complicated.

 

59. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains the coded object modules of the program to be assembled.

60. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned

Answer: d
Explanation: The assembly level programming is more advantageous than the machine level programming.